The present invention relates to an integrated scheme for predicting yield of semiconductor devices.
Within-chip variability of critical features such as polycrystalline silicon (poly) lines due to limitations of manufacturing processes is a major cause of device variability and product yield loss in semiconductor devices. A significant fraction of this variability is a deterministic function of local layout patterns and properties of the manufacturing processes (lithography, etch, etc.). In particular, optical proximity effects on the poly layer can degrade transistor parameters or even lead to catastrophic failures, such as shorts or opens. Gate length variability is the main source of circuit-level variation and a major performance and yield limiter. Sensitivity of transistor performance to gate critical dimension (CD) is a strong function of transistor architecture and, thus, the front-end manufacturing process.
Reducing circuit-level variability can be achieved at two levels:
(a) in the design phase, by applying Optical Proximity Correction (OPC) techniques to improve pattern reproduction.
(b) in the process development or manufacturing phase of a product, by reducing sensitivity of active devices to pattern fidelity.
Optical Proximity Correction serifs (or hammerheads) that enhance pattern resolution on wafers for deep submicron layouts are particularly vulnerable to the quality of the mask making process. Placement on line ends and in layout corners subjects the serifs to process-induced rounding. Also, the designed serif size, often much smaller than that of MOSFET channels and connecting lines, is close to the mask resolution limits and therefore difficult to control. At the same time, for layouts of extreme densities, such as those in high performance SRAM cells, device tolerance for line end rounding requires highly accurate serif reproduction. The differences between the drawn and on-mask serif size and shape, as well as intramask variation, may no longer guarantee transistor performance within specified limits. However, state of the art simulation tools assume a perfect process of pattern transfer from layout to mask, with no margin for variations of OPC serif size. While the latitude of such a process could impact transistor parameters, no work has been done to link its accuracy to the final yield loss due to MOSFET degradation. Only the MOSFET parameters are used to determine device yield.
Photolithographic simulations can approximate photoresist patterns. In such a simulation, the pattern is first drawn. Then optical simulation can be used to simulate the photoresist patterns. The photoresist patterns can be used to determine the gate pattern.
The photolithographic simulations (drawing of pattern, optical simulation, and determination of gate pattern) could not be easily, or previously coupled with systems for determining device yield (determining MOSFET parameters, then determining device yield from the parameters) because there was no way to transform the results of the photolithographic simulations into a form usable by the software for determining device yield.
In a first aspect, the present invention is a method for determining device yield of a semiconductor device design, including determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter.
In a second aspect, the present invention is a method of preparing a semiconductor device, including determining the device yield of a semiconductor device design, and producing a device corresponding to the semiconductor device design.
In a third aspect, the present invention is a computer program product on a computer readable medium, for determining device yield, including code in the computer readable medium for causing a computer to determine statistics of at least one MOSFET parameter from a gate pattern, and code in the computer readable medium for causing a computer to calculate device yield from the at least one MOSFET parameter.